The present invention provides method and circuitry for converting a differential signal to a single-ended signal for high speed circuit applications. Broadly, the invention takes advantage of the regenerative action of a CMOS latch to convert a differential logic signal to a single-ended one with minimum delay. According to a specific embodiment of the invention, the state of a CMOS latch is switched by current pulses generated by a differential pair with C3MOS input levels. The latch is made of CMOS inverters with transistors having standard channel sizes. When a pulse is applied to either side of the latch, a fast and nearly symmetric transition will occur due to the regenerative nature of the latch, yielding a single-ended rail-to-rail CMOS level output signal with minimum delay and near 50% duty cycle.
Accordingly, in one embodiment, the present invention provides a circuit for converting a differential logic signal to a single-ended logic signal, including: a differential input stage coupled to receive the differential logic signal and configured to steer current into a first output branch or a second output branch in response to the differential logic signal; a first output transistor coupled to the first output branch; a second output transistor coupled to the second output branch; and a CMOS latch coupled between the first output transistor and the second output transistor.
In a more specific embodiment of the present invention the CMOS latch includes a first CMOS inverter having an input and an output; and a second CMOS inverter having an input coupled to the output of the first CMOS inverter, and an output coupled to the input of the CMOS inverter, wherein channel sizes of transistors inside each CMOS inverter are designed to achieve optimum switching in both directions.
In another embodiment, the present invention provides a CMOS circuit comprising: a first circuit implemented in C3MOS logic wherein logic levels are signaled by current steering in one of two or more branches in response to a differential input signal; a differential signal to single-ended signal converter coupled to the first circuit, the converter having a CMOS latch that is configured to switch states in response to a self-regulating current pulse that is generated in response to the differential input signal, thereby converting the differential signal from the first circuit to a single-ended CMOS logic signal; and a second circuit coupled to the converter to receive the single-ended CMOS logic signal and implemented in standard CMOS logic wherein substantially zero static current is dissipated.
In yet another embodiment the present invention provides a method of converting a differential logic signal to a single-ended logic signal including receiving a differential logic signal at inputs of a differential input circuit; generating a current pulse at one of two outputs of the differential pair in response to the differential logic signal; and switching the state of a regenerative CMOS latch in response to the current pulse.
The detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the signal level converter of the present invention.